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IBM, Samsung, and GlobalFoundries have developed the 5nm chip-making process
By John Law & Liu Hongzuo - on 6 Jun 2017, 11:00am

IBM, Samsung, and GlobalFoundries have developed the 5nm chip-making process

Wafer of chips with 5nm silicon nanosheet transistors. Image credit: IBM.

Tech giants IBM, Samsung, and GlobalFoundries (chip manufacturers for Qualcomm, AMD, etc.) recently developed a process for manufacturing 5-nanometer (nm) chips. Just two years ago, IBM developed a 7nm test chip with 20 billion transistors.

According to IBM’s press statement, the new manufacturing process lends an increase in chip performance – areas such as cognitive computing, IoT devices, and cloud-based, data-sensitive applications will stand to gain. Also, the smaller chip size would ideally benefit mobile devices (such as smartphones) by letting them get up to three times longer battery life before requiring a charge.

Preparing test wafers with 5nm silicon nanosheet transistors.

An IBM-led research team accomplished this feat by using stacks of silicon nanosheets as the device structure of the transistor. This 5nm manufacturing process does not use the FinFET architecture we’ve become familiar with – instead, it uses a technique called GAAFET (gate-all-around transistor). Ars Technica has detailed the differences in chip-making between both FinFET and GAAFET architecture here.

“For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential,” said Arvind Krishna, senior vice president, Hybrid Cloud, and director, IBM Research. “That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry, and brings them to market in technologies like mainframes and our cognitive systems.”

Silicon nanosheet transistors at 5nm.

IBM said the nanosheet-based 5nm chip can offer up to 40 percent performance improvement over existing 10nm chips when both are given the same level of power. If the power is scaled down to match the older chip, it saves 75 percent of power while outputting the same level of performance.

Source: IBM, Ars Technica.